1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to a semiconductor memory device that can simultaneously achieve both process consistency with logic transistors, and cost reduction.
2. Description of the Related Art
With the progress of circuit pattern miniaturization, it has become possible to integrate a greater number of transistors on one chip and to endow the chip with a greater number of functions correspondingly. Compared with a processor/memory independent chip structure, on-chip memories each mounted together with a processor in mixed form on the same chip are superior in terms of both data transfer rate and electric power consumption. As mobile apparatus, including hand-held telephones and personal data assistants (PDAs), is more advanced in function, the role that on-chip memories are to play is becoming more important since greater importance is attached to simultaneous realization of a more advanced function and less power consumption. Conventionally, SRAMs have been exclusively used because of their manufacturing process consistency with logic transistors. A conventional technology associated with an on-chip low-power SRAM is described in the technical paper “M. Yamaoka et al., IEEE International Solid-State Circuit Conferences, 2004, pp. 494-495.”
DRAMs are known as memories higher than SRAMs in integration density. However, DRAMS are low in process consistency with logic transistors. This is because DRAMs adopt the principles of operation in which they store electric charges into capacitors, and thus because the introduction not only of Ta2O5 (tantalum pentoxide) or other highly dielectric materials, but also of stereographic construction, is absolutely needed to ensure capacitance of at least a fixed level with a finer-cell area. A memory element structure called the gain cell is proposed as a DRAM that can operate without taking special capacitor construction. This memory element structure performs a memory function by storing an electric charge into a memory node via a write transistor and utilizing a change in the threshold voltage of a separately provided read transistor according to the stored charge. For the sake of description, two types of memory cell equivalent circuits, both employing gain cell construction, are shown in FIGS. 1A and 1B. FIG. 1A shows two-transistor construction, and FIG. 1B shows three-transistor construction. The following description uses the words “read transistor”, “write transistor”, and “select transistor”, in the relevant relationship between FIGS. 1A, 1B. Conventional technologies associated with the present invention are described in the technical papers “H. Shichijo et al., Conference on Solid-State Devices and Materials, 1984, pp. 265-268” and “S. Shukuri et al., IEEE International Electron Devices Meeting, 1992, pp. 1006-1008.” The former of the above two papers discusses a write transistor that uses polycrystalline silicon, and the latter, a read transistor that uses polycrystalline silicon. Also, a gain cell memory that uses polycrystalline silicon is discussed in the technical paper “T. Osabe et al., IEEE International Electron Devices Meeting, 2000, pp. 301-304.” This paper describes a gain cell memory that ensures a sufficient hold time by utilizing the fact that a TFT using an ultrathin polycrystalline silicon film to form a channel is extremely small in leakage current.